1. Field of the Invention
The present invention relates to a storage circuit usable in a delay circuit which may be used to generate surround-sounds in an audio instrument.
2. Description of the Prior Art
Conventional audio instruments generate surround-sounds by attenuating and superimposing reproduced sounds with a time delay. Reproduce modes include stadium mode, church mode and other modes in which reproduced sounds are superimposed on top of one another with a time delay through different techniques.
A delay circuit used for such applications is exemplified in FIG. 1. The delay circuit includes an A/D converter 10 for temporarily converting analog reproduction signals into digital data which are in turn stored in a memory 12. The delay circuit also includes a D/A converter 14 for converting the digital data read out from the memory 12 back into analog data. If there is a difference between write time and read time in the memory 12, it will be a delay time.
More particularly, a delay time signal can be obtained by writing data into the memory 12 at an address and reading out data from the memory 12 at another address spaced away from the first-mentioned address by a given time period (i.e., a location at which the other data has been written before the given time period).
In the church mode, for example, reproduced sounds are required to provide many echoes as in an actual church. Thus, a great number of reproduction signals must be generated with a plurality of short delay times to attenuate and superimpose each set of reproduction signals one on top of another.
In order to provide four different types of delay time data, for example, data will be readout at four different addresses (READs 1-4) before a data writing cycle is repeated while sequentially changing the address, as shown in FIG. 2.
However, such a process must do four read addressings and one write addressing through one cycle. If the input data clock is sufficiently slow, the five addressings do not raise any problem. However, the A/D converter 10 used in the delay circuit of FIG. 1 has a very fast clock since it functions to output signals in the form of a pulse string through the conventional over-sampling action. When five addressings are to be carried out within one cycle, it will exceed the capacity of the memory cell.